1. Field of the Invention
This invention relates generally to field effect transistor structures and, more particularly, to high performance MOSFET transistor structures and a method for making the same.
2. Discussion of the Related Art
A field-effect transistor (FET) is a solid state amplifying device. Amplification in the device occurs when the current through two terminals is varied by an electric field arising from voltage applied to a third terminal. The FET is thus a voltage controlled device. In an insulated-gate (IG) type of FET, the controlling field appears at an insulating layer. Variations in the field cause corresponding variations in the current through the device. Because the input or control voltage is applied across an insulator, the FET is further characterized by a high input impedance.
In the IGFET, the channel current is controlled by a voltage at a gate electrode which is isolated from the channel by an insulator. In one common configuration, an oxide layer is grown or deposited on the semiconductor surface, and a polysilicon gate electrode is deposited onto this oxide layer. The resulting structure is commonly called a metal-oxide-semiconductor (MOS) structure. If the device includes a source and drain, it represents a MOS transistor or MOSFET. The MOSFET has the advantage of extremely high input impedance between the gate and source electrodes, since these terminals are separated by an oxide layer. The general term IGFET includes devices in which the insulator may be some material other than an oxide layer.
In further discussion of the above, a MOSFET can be either a depletion device or an enhancement device. The depletion device MOSFET is one in which a channel exists at zero gate voltage. The depletion device is thus referred to as a normally on device. On the other hand, the enhancement device MOSFET is a device which requires a gate voltage to induce a channel and is further referred to as a normally off device. Furthermore, the MOSFET is either an n-channel or a p-channel device, depending upon the carrier type in the channel.
In an n-channel device, the source and drain regions include n.sup.+ regions diffused into a high-resistivity p substrate. The channel region may be either a thin diffused n layer or an induced inversion region. In an n-type diffused channel device, the effect of the electric field is to raise or lower the conductance of the channel by either depleting or enhancing the electron density in the channel. When a positive voltage is applied to the gate (i.e., at the oxide-semiconductor interface), an electric field in the oxide layer exists between positive charge on the gate electrode and negative charge in the semiconductor. The negative charge is composed of an accumulation of mobile electrons into the channel and fixed ionized acceptor atoms in the depleted p material. If the gate-to-source voltage is positive, the conductivity of the channel is enhanced, while a negative gate voltage tends to deplete the channel of electrons. Thus a diffused-channel MOSFET can be operated in either the depletion or enhancement modes.
In an induced-channel MOSFET transistor, for an n-channel device, there is no diffused n-type region existing between source and drain at equilibrium. When a positive gate voltage is applied to the structure, a depletion region is formed in the p material, and a thin layer of mobile electrons is drawn from the source and drain into the channel. Where the mobile electrons dominate, the material is effectively n-type. This is called an inversion layer, since the material was originally p-type. Once the inversion layer is formed near the semiconductor surface, a conducting channel exists from the source to the drain. The operation of the device is then quite similar as discussed above. The channel conductance is controlled by the field in the insulator, but the magnitude of this field varies along the channel (V.sub.GX) from the voltage at the drain (V.sub.GS -V.sub.DS) to the voltage at the source (V.sub.GS). Since a positive voltage is required between the gate and each point x in the channel to maintain inversion, a large enough value of V.sub.DS can cause the field in the insulator to go to zero at the drain. As a result there is a small depleted region at the drain end of the channel through which electrons are injected in the saturation current. Once pinch-off is reached, the saturation current remains essentially constant. A p-channel MOSFET is similar to the n-channel, however, the conductivity types are reversed.
In addition, in the present state of the art, miniaturization of field-effect transistor device dimensions is continually being sought. Several limitations on miniaturization of FET devices have been encountered. For instance, it is extremely difficult to form FETs with the channel other than parallel to the substrate. Thus, the size of the transistor cannot generally be made smaller than the size of the gate or the channel. Furthermore, as the channel is made small, adverse effects on transistor performance occur. Modifications of existing techniques for fabrication of FET device structures introduce performance degradations into fabricated devices and limit performance characteristics of the same.
In the fabrication of very large scale integrated circuits (VLSI) and ultra large scale integrated circuits (ULSI), it would be desirable to improve upon device performance, in terms of, transistor speed, low power consumption, leakage current, as well as, provide a higher device density.
In prior known transistor structures, grown or deposited oxides have been known to be used for separating a polysilicon layer from an underlying substrate. A disadvantage of such oxides is that oxides have a relatively high dielectric constant or K-value. In particular, oxides have a dielectric constant in the range of 3.9-4.2. In addition, with respect to grown oxides, grown oxides are further undesirable in that they introduce encroachment issues such LOCOS bird's beak to a semiconductor structure.
Looking at a semiconductor memory device, U.S. Pat. No. 5,373,170, describes an SRAM cell with thin film transistors. The SRAM cell employs the use of grown oxides in the formation of thin film transistor devices. A transistor device is formed above a polysilicon layer which is above an active region of the substrate, including a source region, a channel region, and a drain region. The thin-film transistor of the '170 patent, however, suffers from not being built all in the same plane. As a result, the transistor of '170 requires extra space due to its non-planarity.
A depth of focus for a patterning exposure step in a semiconductor device fabrication process is an important consideration during a patterning step, especially for defining small device features, in the tenths of microns range. For instance, if during a patterning exposure, the topology of the substrate being exposed is substantially (and/or partially) outside of a depth of focus of an exposure apparatus, then it is difficult to accurately form the desired transistor devices. The fabrication process is thus degraded.
Fabrication of integrated circuit devices also involves numerous process steps which add to a cost of manufacturing the integrated circuit devices. It would thus be desirable to provide an improved method of making integrated circuit devices by reducing the number of process steps.